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Disambiguation of "Chiang, Patrick Yin"

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A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS.

, , , , and . IEEE J. Solid State Circuits, 45 (4): 899-908 (2010)

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Yin-Ru Chiang

Chiang Liang

Chiang Mai

Joanna Chiang

Lu Yin

 

Other publications of authors with the same name

A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system., , , , and . ASICON, page 1-4. IEEE, (2015)Anti-Gan: Discriminating 3D reconstructed and real faces for robust facial Identity in Anti-spoofing Generator Adversarial Network., , and . ISSPIT, page 1-8. IEEE, (2020)All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS., and . CICC, page 1-4. IEEE, (2011)A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces., , , , and . CICC, page 1-4. IEEE, (2014)Energy-aware Retinaface: A Power Efficient Edge-Computing SOC for Face Detector in 40nm., , and . ASICON, page 1-4. IEEE, (2021)dToF LIDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128x80 SPAD Sensor, and ML-Based Object Detection for Adaptive Beam-Steering., , , , , , , , , and 9 other author(s). CICC, page 1-2. IEEE, (2023)Low-Noise Broadband CMOS TIA Based on Multi-Stage Stagger-Tuned Amplifier for High-Speed High-Sensitivity Optical Communication., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3676-3689 (2019)A Framework for Compressive-Sensing of 3D Point Clouds., , and . CIS, page 69-72. IEEE, (2016)Rate-adaptive compressed-sensing and sparsity variance of biomedical signals., , , , and . BSN, page 1-6. IEEE, (2015)Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS., , , and . CICC, page 1-4. IEEE, (2011)