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Scan chain encryption for the test, diagnosis and debug of secure circuits., , , , , и . ETS, стр. 1-6. IEEE, (2017)Analyzing testability from behavioral to RT level., , и . ED&TC, стр. 158-165. IEEE Computer Society, (1997)High-level synthesis for easy testability., , и . ED&TC, стр. 198-206. IEEE Computer Society, (1995)On Preventing SAT Attack with Decoy Key-Inputs., , , и . ISVLSI, стр. 114-119. IEEE, (2021)Resynthesis-based Attacks Against Logic Locking., , , , , и . ISQED, стр. 1-8. IEEE, (2023)New testing procedure for finding insertion sites of stealthy hardware trojans., , , , и . DATE, стр. 776-781. ACM, (2015)A secure scan design methodology., , , и . DATE, стр. 1177-1178. European Design and Automation Association, Leuven, Belgium, (2006)Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model., , , , , , , , , и 3 other автор(ы). FDTC, стр. 1-6. IEEE Computer Society, (2018)A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans., , , , и . IOLTS, стр. 49-54. IEEE, (2014)Laser attacks on integrated circuits: From CMOS to FD-SOI., , , , , , , , , и . DTIS, стр. 1-6. IEEE, (2014)