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POSEIDON: A framework for application-specific Network-on-Chip synthesis for heterogeneous chip multiprocessors.

, , and . ISQED, page 182-188. IEEE, (2011)

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HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures., and . ISQED, page 91-98. IEEE, (2014)Memory-aware circuit overlay NoCs for latency optimized GPGPU architectures., and . ISQED, page 63-68. IEEE, (2016)POSEIDON: A framework for application-specific Network-on-Chip synthesis for heterogeneous chip multiprocessors., , and . ISQED, page 182-188. IEEE, (2011)Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency., , , and . DAC, page 68-71. ACM, (2008)VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip., and . ACM Great Lakes Symposium on VLSI, page 31-36. ACM, (2011)SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures., , , and . DAC, page 81:1-81:6. ACM, (2018)Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors., and . CODES+ISSS, page 129-136. ACM, (2009)Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers., , and . NOCS, page 1-4. IEEE, (2016)SLAM: High Performance and Energy Efficient Hybrid Last Level Cache Architecture for Multicore Embedded Systems., and . ICESS, page 1-7. IEEE, (2019)COMET: A Cross-Layer Optimized Optical Phase Change Main Memory Architecture., , , , and . CoRR, (2023)