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A Dynamic Power Estimation Method for System on Chip Designs.

, и . J. Low Power Electron., 11 (4): 455-466 (2015)

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Pasan Karunaratne

Kamesh Madduri

Sasidhar Maddula

Sasidhar Maddula

Hawis H Madduppa

 

Другие публикации лиц с тем же именем

Verification Components Reuse., , и . J. Comput., 7 (11): 2641-2649 (2012)A Dynamic Power Estimation Method for System on Chip Designs., и . J. Low Power Electron., 11 (4): 455-466 (2015)Test generation based on synthesizable VHDL descriptions., и . EURO-DAC, стр. 446-451. IEEE Computer Society, (1993)