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Design techniques to improve the device write margin for MRAM-based cache memory.

, , , , and . ACM Great Lakes Symposium on VLSI, page 97-102. ACM, (2011)

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An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process., , , , , , , , and . ASICON, page 1-4. IEEE, (2021)Comprehensive Study of Electrode Effect in Metal/CuInP2S6/Metal Heterostructures., , , , , , , , and . Symmetry, 15 (5): 966 (April 2023)Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions., , , , , , , , and . IRPS, page 4. IEEE, (2015)Design techniques to improve the device write margin for MRAM-based cache memory., , , , and . ACM Great Lakes Symposium on VLSI, page 97-102. ACM, (2011)Exploring the use of volatile STT-RAM for energy efficient video processing., , , , and . ISQED, page 81-87. IEEE, (2016)Hardware implementation of KLMS algorithm using FPGA., , , , and . IJCNN, page 2276-2281. IEEE, (2014)A fast low-light multi-image fusion with online image restoration., , , and . ICCE, page 346-347. IEEE, (2013)Stereo panoramic image stitching with a single camera., , , , and . ICCE, page 256-257. IEEE, (2013)Innovative Barrier Metal-Less Metal Gate Scheme Leading to Highly Reliable Cell Characteristics for 8th Generation 512Gb 3D NAND Flash Memory., , , , , , , , , and 4 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2024)A low-area digitalized channel selection filter for DSRC system., , and . VLSI-DAT, page 1-4. IEEE, (2014)