Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network.

Y. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada, and T. Kuroda. ASP-DAC, page 182-183. ACM, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Marek Rei

Rei Sugaya

Rei Thiessen

Claudia Reitz

Extrudierte Fettmatrizes mit retardierter WirkstofffreigabeC. Reitz. Uni Düsseldorf, (2007)

Johannes Reichert

Methodik zur Verbesserung der Ergebnisqualität bei der IT-gestützten Fabrikplanung im Rahmen der digitalen FabrikJ. Reichert. TU Clausthal-Zellerfeld, (2009)

Other publications of authors with the same name

A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application.A. Kosuge, R. Sumikawa, Y. Hsu, K. Shiba, M. Hamada, and T. Kuroda. VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS.R. Sumikawa, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda. ASP-DAC, page 180-181. ACM, (2023)A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network.Y. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada, and T. Kuroda. HCS, page 1-14. IEEE, (2022)A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network.Y. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada, and T. Kuroda. ASP-DAC, page 182-183. ACM, (2023)A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network.D. Li, Y. Hsu, R. Sumikawa, A. Kosuge, M. Hamada, and T. Kuroda. ISCAS, page 1-5. IEEE, (2023)A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA.D. Li, Z. Zhan, R. Sumikawa, M. Hamada, A. Kosuge, and T. Kuroda. IEICE Trans. Electron., 107 (6): 155-162 (2024)

BibSonomy

Disambiguation of "Sumikawa, Rei"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network.

Please choose a person to relate this publication to

Marek Rei

Rei Sugaya

Rei Thiessen

Claudia Reitz

Johannes Reichert

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sumikawa, Rei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network.

Please choose a person to relate this publication to

Marek Rei

Rei Sugaya

Rei Thiessen

Claudia Reitz

Johannes Reichert

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network.