( en | de | ru )

 

Disambiguation of "Rajendran, Jeyavijayan (JV)"

Author of the publication

copydeleteadd this publication to your clipboard
SARLock: SAT attack resistant logic locking.

, , , and . HOST, page 236-241. IEEE Computer Society, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chitra Rajendran

Vidyalakshmi Rajendran

Lawrence Rajendran

Ranjithkumar Rajendran

Raphael Samuel Rajendran

 

Other publications of authors with the same name

SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis., , and . ICCAD, page 1-4. ACM, (2019)DETERRENT: detecting trojans using reinforcement learning., , , , and . DAC, page 697-702. ACM, (2022)Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (9): 2946-2959 (2016)Towards provably-secure performance locking., , , , , and . DATE, page 1592-1597. IEEE, (2018)Routing perturbation for enhanced security in split manufacturing., , , and . ASP-DAC, page 605-510. IEEE, (2017)On designing optimal camouflaged layouts., , and . HOST, page 169. IEEE Computer Society, (2017)Does logic locking work with EDA tools?, , and . USENIX Security Symposium, page 1055-1072. USENIX Association, (2021)SARLock: SAT attack resistant logic locking., , , and . HOST, page 236-241. IEEE Computer Society, (2016)An overview of hardware intellectual property protection.. ISCAS, page 1-4. IEEE, (2017)Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits., , , , , and . ITC, page 1-10. IEEE, (2020)