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Disambiguation of "Theertham, Raviteja"

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A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs.

, , , , , , , , , , and . CICC, page 1-2. IEEE, (2023)

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Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density., , , and . IEEE J. Solid State Circuits, 55 (9): 2429-2442 (2020)A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs., , , , , , , , , and 1 other author(s). CICC, page 1-2. IEEE, (2023)22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors., , , , , , , , , and 3 other author(s). ISSCC, page 390-392. IEEE, (2024)A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth., , , and . VLSI Circuits, page 226-. IEEE, (2019)Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback., and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (4): 1991-1995 (2022)Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs., , and . IEEE J. Solid State Circuits, 57 (11): 3418-3428 (2022)Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators., and . ISCAS, page 1. IEEE, (2020)A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM., , , , , , , and . CICC, page 1-2. IEEE, (2022)