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Другие публикации лиц с тем же именем

Empirical Study of Latency Hiding on a Fine-Grain Parallel Processor., , и . International Conference on Supercomputing, стр. 220-229. ACM, (1993)Limits of Thread-Level Parallelism in Non-numerical Programs., , , и . Inf. Media Technol., 1 (2): 851-859 (2006)Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation., , , и . MEDEA@PACT, стр. 33-40. ACM, (2007)A preactivating mechanism for a VT-CMOS cache using address prediction., , , , и . ISLPED, стр. 247-250. ACM, (2002)Pipeline stage unification: a low-energy consumption technique for future mobile processors., , и . ISLPED, стр. 326-329. ACM, (2003)Maintenance Architecture and Its LSI Implementation of a Dataflow Computer with a Large Number of Processors., , , и . ICPP, стр. 584-591. IEEE Computer Society Press, (1986)The Hardware Architecture of the CODA Real-Time Parallel Processor., , , и . PARCO, стр. 395-402. Elsevier, (1993)Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations., , , и . ISCA, стр. 226-234. IEEE Computer Society, (1986)Efficient vector processing on dataflow supercomputer SIGMA-1., , и . SC, стр. 374-381. IEEE Computer Society, (1988)An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism., , , , и . EUROMICRO, стр. 1432-1440. IEEE Computer Society, (1999)