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A priority forwarding scheme for real-time multistage interconnection networks.

, , , and . RTSS, page 208-217. IEEE Computer Society, (1992)

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Empirical Study of Latency Hiding on a Fine-Grain Parallel Processor., , and . International Conference on Supercomputing, page 220-229. ACM, (1993)Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation., , , and . MEDEA@PACT, page 33-40. ACM, (2007)A preactivating mechanism for a VT-CMOS cache using address prediction., , , , and . ISLPED, page 247-250. ACM, (2002)Pipeline stage unification: a low-energy consumption technique for future mobile processors., , and . ISLPED, page 326-329. ACM, (2003)Limits of Thread-Level Parallelism in Non-numerical Programs., , , and . Inf. Media Technol., 1 (2): 851-859 (2006)Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism., , , , and . IPPS, page 336-343. IEEE Computer Society, (1991)Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation., , , and . Inf. Media Technol., 3 (4): 755-767 (2008)Sequential description and parallel execution language DFCII dataflow supercomputers., , and . ICS, page 57-66. ACM, (1991)Power consumption reduction scheme focusing on the Depth of Speculative Execution., , , and . CIT, page 207-212. IEEE Computer Society, (2008)A priority forwarding scheme for real-time multistage interconnection networks., , , and . RTSS, page 208-217. IEEE Computer Society, (1992)