( en | de | ru )

 

Disambiguation of "Rajendran, Jeyavijayan"

Author of the publication

copydeleteadd this publication to your clipboard
Parallel memristors: Improving variation tolerance in memristive digital circuits.

, , and . ISCAS, page 2241-2244. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chitra Rajendran

Vidyalakshmi Rajendran

Lawrence Rajendran

Ranjithkumar Rajendran

Raphael Samuel Rajendran

 

Other publications of authors with the same name

Security analysis of integrated circuit camouflaging., , , and . CCS, page 709-720. ACM, (2013)Blue team red team approach to hardware trust assessment., , and . ICCD, page 285-288. IEEE Computer Society, (2011)Hardware-based attacks to compromise the cryptographic security of an election system., , , , and . ICCD, page 153-156. IEEE Computer Society, (2016)An Approach to Tolerate Process Related Variations in Memristor-Based Applications., , , and . VLSI Design, page 18-23. IEEE Computer Society, (2011)Parallel memristors: Improving variation tolerance in memristive digital circuits., , and . ISCAS, page 2241-2244. IEEE, (2011)The Cat and Mouse in Split Manufacturing., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (5): 805-817 (2018)Special session: Recent developments in hardware security., , , and . VTS, page 1. IEEE Computer Society, (2018)Hot topic session 9C: Test and fault tolerance for emerging memory technologies., , and . VTS, page 1. IEEE Computer Society, (2014)MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors., , , , and . DATE, page 1-6. IEEE, (2024)Activation of logic encrypted chips: Pre-test or post-test?, , , and . DATE, page 139-144. IEEE, (2016)