( en | de | ru )

 

Disambiguation of "Onodera, Hidetoshi"

Author of the publication

copydeleteadd this publication to your clipboard
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.

, , and . DAC, page 446-451. ACM Press, (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

Other publications of authors with the same name

Post-layout transistor sizing for power reduction in cell-based design., and . ASP-DAC, page 359-365. ACM, (2001)Statistical gate delay model for Multiple Input Switching., , and . ASP-DAC, page 286-291. IEEE, (2008)A functional memory type parallel processor for vector quantization., , , , and . ASP-DAC, page 665-666. IEEE, (1997)BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing., , , , , and . ASP-DAC, page 203-209. ACM, (2019)Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics., , , , , , , and . ICRC, page 1-8. IEEE, (2018)An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing., , , , and . ICRC, page 1-6. IEEE, (2018)Worst-case delay analysis considering the variability of transistors and interconnects., , and . ISPD, page 35-42. ACM, (2007)A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime., , , , , , and . FPL, page 1-4. IEEE, (2006)Performance optimization by track swapping on critical paths utilizing random variations for FPGAS., , , and . FPL, page 503-506. IEEE, (2008)Analysis and comparison of XOR cell structures for low voltage circuit design., , and . ISQED, page 703-708. IEEE, (2013)