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A Multi-Kernel Multi-Code Polar Decoder Architecture., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (12): 4413-4422 (2018)Flexible blocks for high throughput serially concatenated convolutional codes., and . ACM Great Lakes Symposium on VLSI, page 184-187. ACM, (2007)Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding., , , , and . DASIP, page 1-6. IEEE, (2015)An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission., , , , , , and . DATE, page 1479-1484. ACM, (2015)VLSI implementation of SISO arithmetic decoders for joint source channel coding., and . DATE, page 1075-1078. ACM, (2008)Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives., , and . PRIME, page 209-212. IEEE, (2023)Thermal Control for Crossbar-Based Input-Queued Switches., , , and . GLOBECOM, page 1-5. IEEE, (2010)Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures, and . CoRR, (2009)Low-Complexity Video Compression Combining Adaptive Multifoveation and Reuse of High-Resolution Information., , , and . ICIP, page 3153-3156. IEEE, (2006)Approximate Arai DCT Architecture for HEVC., , , and . NGCAS, page 133-136. IEEE, (2017)