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Energy-efficient cache design using variable-strength error-correcting codes., , , , , and . ISCA, page 461-472. ACM, (2011)Rank-aware cache replacement and write buffering to improve DRAM energy efficiency., and . ISLPED, page 383-388. ACM, (2010)DaeMon: Architectural Support for Efficient Data Movement in Disaggregated Systems., , , , , , and . CoRR, (2023)Memory system characterization of deep learning workloads., and . MEMSYS, page 497-505. ACM, (2019)Trading off Cache Capacity for Reliability to Enable Low Voltage Operation., , , , , and . ISCA, page 203-214. IEEE Computer Society, (2008)DaeMon: Architectural Support for Efficient Data Movement in Fully Disaggregated Systems., , , , , , and . Proc. ACM Meas. Anal. Comput. Syst., 7 (1): 16:1-16:36 (March 2023)Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions., , , and . ISCA, page 235-246. ACM, (2015)Reducing cache power with low-cost, multi-bit error-correcting codes., , , , , and . ISCA, page 83-93. ACM, (2010)Improving cache lifetime reliability at ultra-low voltages., , , , and . MICRO, page 89-99. ACM, (2009)Transparent Hardware Management of Stacked DRAM as Part of Memory., , , , and . MICRO, page 13-24. IEEE Computer Society, (2014)