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Disambiguation of "Alioto, Massimo"

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A general model for differential power analysis attacks to static logic circuits.

, , and . ISCAS, page 3346-3349. IEEE, (2008)

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Massimo Viola

Massimo Malagó

Massimo Tallarida

Massimo Moser

Massimo Busin

 

Other publications of authors with the same name

Power-delay trade-offs in SCL gates., and . ISCAS (3), page 249-252. IEEE, (2002)A technique to design high entropy chaos-based true random bit generators., , , , and . ISCAS, IEEE, (2006)Analysis of layout density in FinFET standard cells and impact of fin technology.. ISCAS, page 3204-3207. IEEE, (2010)Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations., , , , and . ISCAS, page 2043-2046. IEEE, (2011)Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS., , , and . ISSCC, page 482-484. IEEE, (2012)A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm., , , and . A-SSCC, page 301-304. IEEE, (2017)Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis., , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 624-633. Springer, (2006)Minimum-Effort Design of Ultra-Low Power Interfaces for the Internet of Things., , and . ICECS, page 105-106. IEEE, (2019)Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (5): 737-750 (2011)Evaluation of energy consumption in RC ladder circuits driven by a ramp input., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (10): 1094-1107 (2004)