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Rethinking Memory System Design (along with Interconnects).. NoCArc@MICRO, page 1. ACM, (2015)LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures., , , , , , , , , and . CoRR, (2017)Self-Optimizing Memory Controllers: A Reinforcement Learning Approach., , , and . ISCA, page 39-50. IEEE Computer Society, (2008)Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance., , , , , , and . PACT, page 25-38. IEEE Computer Society, (2015)Base-delta-immediate compression: practical data compression for on-chip caches., , , , , and . PACT, page 377-388. ACM, (2012)Reducing solid-state drive read latency by optimizing read-retry., , , , , and . ASPLOS, page 702-716. ACM, (2021)Bottleneck identification and scheduling in multithreaded applications., , , and . ASPLOS, page 223-234. ACM, (2012)Flexible reference-counting-based hardware acceleration for garbage collection., , and . ISCA, page 418-428. ACM, (2009)Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques., , , , , , and . ISCA, page 638-651. IEEE, (2020)Utility-based acceleration of multithreaded applications on asymmetric CMPs., , , and . ISCA, page 154-165. ACM, (2013)