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Test power reductions through computationally efficient, decoupled scan chain modifications., and . IEEE Trans. Reliab., 54 (2): 215-223 (2005)Efficient RT-Level Fault Diagnosis., and . J. Comput. Sci. Technol., 20 (2): 166-174 (2005)Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (2): 266-280 (2022)Logic Locking With Provable Security Against Power Analysis Attacks., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (4): 766-778 (2020)Guest Editorial: Special Issue On Emerging Technologies in Computer Design., and . IEEE Trans. Emerg. Top. Comput., 9 (1): 5-6 (2021)Embracing Graph Neural Networks for Hardware Security (Invited Paper)., , , and . CoRR, (2022)Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime., , , , and . CoRR, (2019)Extending the Applicability of Parallel-Serial Scan Designs., , and . ICCD, page 200-203. IEEE Computer Society, (2004)ScanSAT: unlocking obfuscated scan chains., , , , , and . ASP-DAC, page 352-357. ACM, (2019)Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition., and . ITC, page 1-10. IEEE, (2018)