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Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime., , , , and . CoRR, (2019)Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access., , , and . ICCAD, page 1-8. ACM, (2019)Revival of partial scan: Test cube analysis driven conversion of flip-flops., and . VTS, page 260-265. IEEE Computer Society, (2011)Design and analysis of ring oscillator based Design-for-Trust technique., , , and . VTS, page 105-110. IEEE Computer Society, (2011)Parity-based output compaction for core-based SOCs logic testing., and . ETW, page 15-20. IEEE Computer Society, (2003)Reconciling the IC test and security dichotomy., , , , , , and . ETS, page 1-6. IEEE Computer Society, (2013)Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology., , and . ISQED, page 1-8. IEEE, (2024)Obfuscation of FSMs for Secure Outsourcing of Neural Network Inference onto FPGAs., , and . ISCAS, page 1-5. IEEE, (2024)Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques., , and . DATE, page 1166-1171. IEEE, (2021)Security Closure of IC Layouts Against Hardware Trojans., , , , , , , , , and . ISPD, page 229-237. ACM, (2023)