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Disambiguation of "Shanbhag, Naresh R."

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Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures.

, and . IEEE Trans. Signal Process., (2021)

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Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

Other publications of authors with the same name

A voltage overscaled low-power digital filter IC., and . IEEE J. Solid State Circuits, 39 (2): 388-391 (2004)System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-Vt Computing., , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (9): 726-730 (2014)A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , and . IEEE J. Solid State Circuits, 53 (11): 3163-3173 (2018)Analytical estimation of signal transition activity from word-level statistics., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (7): 718-733 (1997)Linear turbo equalization analysis via BER transfer and EXIT charts., , and . IEEE Trans. Signal Process., 53 (8-1): 2883-2897 (2005)Area-efficient high-throughput MAP decoder architectures., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 921-933 (2005)A Study of BER-Optimal ADC-Based Receiver for Serial Links., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (5): 693-704 (2016)Signal Processing for High-Speed Links., , and . Handbook of Signal Processing Systems, Springer, (2013)A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array., , and . ESSCIRC, page 263-266. IEEE, (2017)A sphere decoding approach for the vector Viterbi algorithm., , , and . ACSCC, page 114-118. IEEE, (2012)