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NetBouncer: Active Device and Link Failure Localization in Data Center Networks.

, , , , , , , and . NSDI, page 599-614. USENIX Association, (2019)

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An Optimal Design for Parallel Test Generation Based on Circuit Partitioning., and . VLSI Design, page 297-300. IEEE Computer Society, (1994)Pattern-directed circuit virtual partitioning for test power reduction., , and . ITC, page 1-10. IEEE Computer Society, (2007)Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis., , and . Asian Test Symposium, page 86-. IEEE Computer Society, (2002)Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects., , , and . Asian Test Symposium, page 297-302. IEEE Computer Society, (2011)A Hybrid Flow for Memory Failure Bitmap Classification., , , , , , and . Asian Test Symposium, page 314-319. IEEE Computer Society, (2012)TM: a new and simple topology for interconnection networks., , and . J. Supercomput., 66 (1): 514-538 (2013)Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (5): 450-454 (2007)Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing., , and . VTS, page 1-6. IEEE, (2020)Cooperative power scheduling for a network of MIMO links., , and . IEEE Trans. Wirel. Commun., 9 (3): 939-944 (2010)Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture., , , , and . ATS, page 299-306. IEEE, (2006)