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Disambiguation of "Kim, Yong-Bin"

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A novel 32-bit scalable multiplier architecture.

, , and . ACM Great Lakes Symposium on VLSI, page 241-244. ACM, (2003)

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Yong Bin Sun

Se Bin Kim

Ok Bin Kim

Sang-Bin Kim

Yong-Ho Kim

 

Other publications of authors with the same name

Low power 8T SRAM using 32nm independent gate FinFET technology., , and . SoCC, page 247-250. IEEE, (2008)A fast and precise interconnect capacitive coupling noise model., and . ISCAS (2), page 873-876. IEEE, (2004)A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap., and . ISOCC, page 244-245. IEEE, (2017)8Gb/s capacitive low power and high speed 4-PWAM transceiver design., , and . ACM Great Lakes Symposium on VLSI, page 33-38. ACM, (2010)A low stand-by power start-up circuit for SMPS PWM controller., and . ACM Great Lakes Symposium on VLSI, page 251-254. ACM, (2012)A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers., and . ACM Great Lakes Symposium on VLSI, page 311-316. ACM, (2014)An area efficient low power high speed S-Box implementation using power-gated PLA., and . ACM Great Lakes Symposium on VLSI, page 93-94. ACM, (2014)Guest Editors' Introduction: Clockless VLSI Systems., , and . IEEE Des. Test Comput., 20 (6): 5-8 (2003)ProSight PTM 2.0: improved protein identification and characterization for top down mass spectrometry., , , , , , , , , and . Nucleic Acids Res., 35 (Web-Server-Issue): 701-706 (2007)Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset., , and . ICCD, page 320-325. IEEE Computer Society, (2011)