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Disambiguation of "Reddy, Sudhakar M."

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Genetic algorithm based approach for segmented testing.

, , , , and . DSN Workshops, page 85-90. IEEE Computer Society, (2011)

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Sudhakar Peddireddi

Padhmanand Sudhakar

Edamakanti Chandrakanth Reddy

Malgi Prasad Reddy

Martin Reddy

 

Other publications of authors with the same name

Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (1): 121-129 (2009)Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (9): 1424-1428 (2009)TOV: Sequential Test Generation by Ordering of Test Vectors., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 454-465 (2010)Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (2): 398-403 (2008)Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1170-1175 (2006)On synchronizable circuits and their synchronizing sequences., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (9): 1086-1092 (2000)Theorems for identifying undetectable faults in partial-scan circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (8): 1092-1097 (2003)Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (6): 706-714 (2002)Techniques for minimizing power dissipation in scan and combinational circuits during test application., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (12): 1325-1333 (1998)Worst-case and average-case analysis of n-detection test sets and test generation strategies., and . IET Comput. Digit. Tech., 1 (4): 353-363 (2007)