( en | de | ru )

 

Disambiguation of "Öberg, Johnny"

Author of the publication

copydeleteadd this publication to your clipboard
Competence Networks in the Era of CPS - Lessons Learnt in the ICES Cross-Disciplinary and Multi-domain Center.

, , , , , , , , , , and . CyPhy/WESE, volume 11971 of Lecture Notes in Computer Science, page 264-283. Springer, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Heidrun Oberg

Johnny Hioe

Johnny Hioe

Johnny Kim

Johnny Leo

 

Other publications of authors with the same name

An improved transmission scheme for error-prone inter-chip network-on-chip communication links implemented on FPGAs., and . FPGAworld, page 8:1-8:6. ACM, (2013)Toward a scalable test methodology for 2D-mesh Network-on-Chips., and . DATE, page 367-372. EDA Consortium, San Jose, CA, USA, (2007)Hardware/software partitioning and minimizing memory interface traffic., , , , and . EURO-DAC, page 226-231. IEEE Computer Society, (1994)Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite., , and . NORCHIP, page 1-6. IEEE, (2014)Grammar-Based Hardware Synthesis of Data Communication Protocols., , and . ISSS, page 14-19. ACM / IEEE Computer Society, (1996)Revolver: A High-Performance MIMD Architecture for Collision Free Computing., and . EUROMICRO, page 10301-. IEEE Computer Society, (1998)From Simulink to NoC-based MPSoC on FPGA., and . DATE, page 1-4. European Design and Automation Association, (2014)Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller., , and . NORCAS, page 1-6. IEEE, (2017)Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAs., , and . NORCAS, page 1-6. IEEE, (2017)Artificial neural network emulation on NOC based multi-core FPGA platform., , and . NORCHIP, page 1-4. IEEE, (2012)