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Cache Array Architecture Optimization at Deep Submicron Technologies.

, , and . ICCD, page 320-325. IEEE Computer Society, (2004)

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Cache Array Architecture Optimization at Deep Submicron Technologies., , and . ICCD, page 320-325. IEEE Computer Society, (2004)Memory performance prediction for high-performance microprocessors at deep submicrometer technologies., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1705-1718 (2006)