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Disambiguation of "Jha, Niraj K."

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Architectures for efficient face authentication in embedded systems.

, , , and . DATE Designers' Forum, page 1-6. European Design and Automation Association, Leuven, Belgium, (2006)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Deepti Jha

Development of a new cell penetrating peptide: design, synthesis and applications = Entwicklung eines neuen zell-penetrierenden Peptids. Uni Tübingen, (2009)

Niraj Upadhayaya

Vandana Jha

Abhinand Jha

Susmit Jha

 

Other publications of authors with the same name

Detecting Multiple Faults in CMOS Circuits.. ITC, page 514-519. IEEE Computer Society, (1986)Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption., and . ESA/VLSI, page 63-69. CSREA Press, (2004)Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring., and . EURO-DAC, page 350-354. IEEE Computer Society, (1990)FTQLS: Fault-Tolerant Quantum Logic Synthesis., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (6): 1350-1363 (2014)Editorial.. IEEE Trans. Very Large Scale Integr. Syst., 15 (3): 249-261 (2007)TAO: regular expression-based register-transfer level testability analysis and optimization., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 824-832 (2001)Automatic Test Generation for Combinational Threshold Logic Networks., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (8): 1035-1045 (2008)Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation., and . IEEE Trans. Very Large Scale Integr. Syst., 25 (9): 2616-2624 (2017)FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations., and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2462-2475 (2014)Analytical Modeling of the SMART NoC., and . IEEE Trans. Multi Scale Comput. Syst., 3 (4): 242-254 (2017)