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A Fault Injection Technique for VHDL Behavioral-Level Models.

, , and . IEEE Des. Test Comput., 13 (4): 24-33 (1996)

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The Analysis of the Faulty Behavior of Synchronous Neural Networks., and . IEEE Trans. Computers, 40 (12): 1424-1429 (1991)Concurrent testing of VLSI circuits using conservative logic., , and . ICCD, page 60-65. IEEE Computer Society, (1990)Using statistics of the extremes for software reliability analysis of safety critical systems., , and . ISSRE, page 355-363. IEEE Computer Society, (1998)Coverage Estimation Using Statistics of the Extremes for When Testing Reveals No Failures., , and . IEEE Trans. Computers, 51 (1): 3-12 (2002)A Fault Injection Technique for VHDL Behavioral-Level Models., , and . IEEE Des. Test Comput., 13 (4): 24-33 (1996)An Integrated Design Environment for Performance and Dependability Analysis., , , , , and . DAC, page 184-189. ACM Press, (1997)The Quantitative Safety Assessment for Safety-Critical Software., and . SEW, page 150-162. IEEE Computer Society, (2005)Bit-slice logic interleaving for spatial multi-bit soft-error tolerance., , , and . DSN, page 141-150. IEEE Computer Society, (2010)Determining the expected time to unsafe failure., , , and . HASE, page 17-24. IEEE Computer Society, (2000)Compacting randomly generated test sets., , , and . ICCD, page 153-156. IEEE Computer Society, (1990)