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Disambiguation of "Chiang, Ping-Chuan"

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Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 55 (4): 1086-1095 (2020)

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Ping-Ping Tsai

Shih-yu Chuang

Jen-Yang Chuang

Mei-Ling Chuang

Jing-Jing Chuang

 

Other publications of authors with the same name

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS., , , , and . ISSCC, page 42-43. IEEE, (2014)A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET., , , , , , , , , and 6 other author(s). ISSCC, page 274-276. IEEE, (2018)100Gb/s ethernet chipsets in 65nm CMOS technology., , , , , and . ISSCC, page 120-121. IEEE, (2013)Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 55 (4): 1086-1095 (2020)56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS., , and . VLSIC, page 118-. IEEE, (2015)A 112-GB/S PAM4 Transmitter in 16NM FinFET., , , , , , , , , and 3 other author(s). VLSI Circuits, page 45-46. IEEE, (2018)A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET., , , , , , , , , and 9 other author(s). CICC, page 1-8. IEEE, (2019)A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension., , , and . ISOCC, page 120-123. IEEE, (2011)50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET., , , , , , , , , and 1 other author(s). ECOC, page 1-4. IEEE, (2020)