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Incremental hierarchical memory size estimation for steering of loop transformations.

, , , , and . ACM Trans. Design Autom. Electr. Syst., 12 (4): 50 (2007)

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Nonlinear transformations for high level regular array ASIC synthesis., , and . VLSI Signal Processing, 4 (4): 259-268 (1992)Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures., , , , , , , , , and . VLSI Signal Processing, 9 (1-2): 49-65 (1995)System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs., , , and . VLSI Signal Processing, 18 (1): 39-50 (1998)Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback., , , , and . DAC, page 327-332. ACM Press, (1999)Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures., , , , and . IEEE Trans. Computers, 58 (3): 311-321 (2009)Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations., , , , and . ICICDT, page 1-4. IEEE, (2014)Accuracy of Quasi-Monte Carlo technique in failure probability estimations., , , , and . ICICDT, page 1-4. IEEE, (2016)Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code, , , and . CoRR, (2007)Systematic intermediate sequence removal for reduced memory accesses., , , and . SCOPES, volume 235 of ACM International Conference Proceeding Series, page 51-60. (2007)Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes., , , and . ACM Trans. Design Autom. Electr. Syst., 19 (1): 4:1-4:30 (2013)