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DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning.

, , , , and . IPDPS, page 1-11. IEEE, (2020)

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Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors., and . IEEE Micro, 25 (1): 41-49 (2005)10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs., , , , and . ICECS, page 577-580. IEEE, (2018)3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores., , and . ICCD, page 413-418. IEEE Computer Society, (2012)An Energy-Efficient Network-on-Chip Design using Reinforcement Learning., and . DAC, page 47. ACM, (2019)Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs., , , , , and . IPDPS Workshops, page 876-883. IEEE, (2013)NBTI aware workload balancing in multi-core systems., , , and . ISQED, page 833-838. IEEE Computer Society, (2009)ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects., , , and . ICCAD, page 1-9. IEEE, (2023)Flumen: Dynamic Processing in the Photonic Interconnect., , , and . ISCA, page 75:1-75:13. ACM, (2023)Parallel electro-optical rule-based system for fast execution of expert systems., and . ISCA, page 427. ACM, (1992)IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores., , , and . ISCA, page 589-600. ACM, (2019)