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Disambiguation of "de Lima Kastensmidt, Fernanda Gusmão"

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Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.

, , , , , and . VLSI-SoC, page 78-83. IEEE, (2007)

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Daiana de Lima Morales

Isabel Arruda Matheos de Lima

Pedro Milanez de Lima Almeida

Joana Helena Esteves de Lima

Marcelo de Lima Leal Ferreira

 

Other publications of authors with the same name

Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies., , , , , and . VLSI-SoC, page 78-83. IEEE, (2007)A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip., , , , , , , and . IEEE Trans. Computers, 57 (9): 1202-1215 (2008)Single event transients in combinatorial circuits., , , and . SBCCI, page 121-126. ACM, (2005)Generation and Propagation of Single Event Transients in CMOS Circuits., , , and . DDECS, page 198-203. IEEE Computer Society, (2006)Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approaches., and . SBCCI, page 1-6. IEEE, (2013)Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies., , , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-16. Springer, (2007)A multiple bit upset tolerant SRAM memory., , , and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 577-590 (2003)Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity., , , , , , and . VLSI-SoC, page 1-6. IEEE, (2014)A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors., , , , , and . ISVLSI, page 485-490. IEEE Computer Society, (2015)Analyzing the effects of the granularity of recomputation based techniques to cope with radiation induced soft errors., , and . WREFT@CF, page 329-338. ACM, (2008)