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65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS., , , и . ISSCC, стр. 384-385. IEEE, (2008)3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 58-59. IEEE, (2017)A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 54-56. IEEE, (2019)Session 8 overview: Digital PLLs and security circuits., , и . ISSCC, стр. 140-141. IEEE, (2017)A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power., , , , , , , и . ISSCC, стр. 240-241. IEEE, (2023)4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability., , , , , , , и . ISSCC, стр. 80-81. IEEE, (2016)A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor., , , , , , , и . IEEE J. Solid State Circuits, 40 (1): 186-194 (2005)A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor., , , , , , , , , и 14 other автор(ы). ISSCC, стр. 2210-2219. IEEE, (2006)Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 2200-2209. IEEE, (2006)A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors., , и . COOL Chips, стр. 1-3. IEEE Computer Society, (2012)