Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Enabling mixed-precision quantized neural networks in extreme-edge devices., , , , and . CF, page 217-220. ACM, (2020)NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs., , , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 11 (3): 18:1-18:24 (2018)HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms., , , , , , , and . DAC, page 1-6. IEEE, (2023)sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor., , , , , , and . BioCAS, page 704-708. IEEE, (2022)4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). ISSCC, page 60-62. IEEE, (2021)Optimization and deployment of CNNs at the edge: the ALOHA experience., , , , , , , , , and 8 other author(s). CF, page 326-332. ACM, (2019)Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors., , , , , , , , , and 11 other author(s). IEEE Wirel. Commun., 30 (4): 162-169 (August 2023)Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors., , , , , , , , , and 11 other author(s). CoRR, (2020)Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 59 (7): 2055-2069 (July 2024)PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters., , , , and . ICECS, page 33-36. IEEE, (2019)