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Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable Architecture

, , , , , , and . Proceedings of the International Conference on Architecture of Computing Systems - Workshop on Dynamically Reconfigurable Systems (DRS), (2007)

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Co-Design of Massively Parallel Embedded Processor Architectures., , , , , , , , , and 2 other author(s). ReCoSoC, page 27-34. Univ. Montpellier II, (2005)Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable Architecture, , , , , , and . Proceedings of the International Conference on Architecture of Computing Systems - Workshop on Dynamically Reconfigurable Systems (DRS), (2007)Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead., and . ARCS Workshops, volume P-81 of LNI, page 132-141. GI, (2006)An Architecture Description Language for Massively Parallel Processor Architectures, , , , , and . Proceedings of the GIITGGMM-Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, (2006)