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Asymmetric aging of clock networks in power efficient designs., , , , and . ISQED, page 484-486. IEEE, (2014)Performance and Reliability Verification of C6201/C6701 Digital Signal Processors., , , and . ICCD, page 521-. IEEE Computer Society, (1999)A Practical Approach to Static Signal Electromigration Analysis., , , and . DAC, page 572-577. ACM Press, (1998)Benchmarks for Interconnect Parasitic Resistance and Capacitance., , , , , , , and . ISQED, page 163-168. IEEE Computer Society, (2003)2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration., , , , , , , , , and 27 other author(s). ISSCC, page 52-54. IEEE, (2020)Enabling DIR(Designing-In-Reliability) through CAD Capabilities., , , , , , , and . ISQED, page 151-156. IEEE Computer Society, (2000)A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs., , , , and . VLSI Design, page 370-375. IEEE Computer Society, (2000)Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs., , , , , and . DATE, page 658-663. IEEE Computer Society / ACM, (1999)