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Disambiguation of "Hironaka, Kazuei"

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Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations.

, , and . FPT, page 1-8. IEEE, (2011)

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Other publications of authors with the same name

The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW., , , , and . HEART, page 15:1-15:4. ACM, (2019)A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search., , , , and . IEICE Trans. Inf. Syst., 106 (11): 1783-1795 (November 2023)Hybrid Network of Packet Switching and STDM in a Multi-FPGA System., , , , and . COOL CHIPS, page 1-6. IEEE, (2021)Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system., , , , and . CANDAR (Workshops), page 277-281. IEEE, (2020)A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems., , and . MCSoC, page 45-52. IEEE, (2022)Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations., , and . FPT, page 1-8. IEEE, (2011)A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System., , , , , , and . MCSoC, page 328-333. IEEE, (2019)Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping., , , , , , , and . FPT, page 349-352. IEEE, (2010)Power Analysis of Directly-connected FPGA Clusters., , , , and . COOL CHIPS, page 1-6. IEEE, (2022)The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator., , and . FPT, page 1-4. IEEE, (2011)