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A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP., , , , , , , , и . ESSCIRC, стр. 95-98. IEEE, (2021)1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing., , , , , , , , , и 1 other автор(ы). ISCAS, стр. 1-5. IEEE, (2023)Compact and low power AES block cipher using lightweight key expansion mechanism and optimal number of S-Boxes., , и . ISPACS, стр. 108-114. IEEE, (2014)Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA., , , , и . CoRR, (2018)Compact and short critical path finite field inverter for cryptographic S-box., , , и . DSP, стр. 775-779. IEEE, (2015)Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor., , и . VLSI-SoC, стр. 95-100. IEEE, (2018)LFSR based S-box for lightweight cryptographic implementation., и . ICCE-TW, стр. 498-499. IEEE, (2015)A 25 TOPS/W High Power Efficiency Deterministic and Split Stochastic MAC (SC-MAC) Design., , и . VLSI-SoC, стр. 1-6. IEEE, (2021)0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications., , , , и . A-SSCC, стр. 141-144. IEEE, (2019)Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency., , , , , , , , , и 2 other автор(ы). Neurocomputing, (2022)