( en | de | ru )

 

Disambiguation of "Fey, Dietmar"

Author of the publication

copydeleteadd this publication to your clipboard
DOSA: Organic Compilation for Neural Network Inference on Distributed FPGAs.

, , , , , and . EDGE, page 43-50. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dietmar Fey

Dietmar Fey

Dietmar Fey

Dirk Fey

Brigitte Fey

 

Other publications of authors with the same name

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM., and . NORCAS, page 1-6. IEEE, (2019)System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration., , , , , and . FPL, page 293-300. IEEE, (2019)Autonomous Driving in the Curriculum of Computer Architecture., , , and . EWME, page 11-16. IEEE, (2018)Bridging the Gap between High-Performance, Cloud and Service-Oriented Computing., , and . FAS*W@SASO/ICAC, page 68-69. IEEE, (2019)Multi-level memristive voltage divider: programming scheme trade-offs., , and . MEMSYS, page 259-268. ACM, (2018)Direct state transfer in MLC based memristive ReRAM devices for ternary computing., and . ECCTD, page 1-5. IEEE, (2020)Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles., and . ISVLSI, page 157-163. IEEE, (2021)Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic., , and . ICECS, page 1-6. IEEE, (2021)Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level., , and . ARCS, volume 14842 of Lecture Notes in Computer Science, page 236-248. Springer, (2024)Programming Reconfigurable Heterogeneous Computing Clusters Using MPI With Transpilation., , , , , and . H2RC@SC, page 1-9. IEEE, (2020)