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RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3053-3064 (2015)Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 15 (5): 531-540 (2007)Integrating Two Logics Into One Crossbar Array for Logic Gate Design., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 68 (8): 2987-2991 (2021)EcoUp: Towards Economical Datacenter Upgrading., , , и . IEEE Trans. Parallel Distributed Syst., 27 (7): 1968-1981 (2016)FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks., , , , , и . HPCA, стр. 553-564. IEEE Computer Society, (2017)P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework., , , и . Asian Test Symposium, стр. 117-120. IEEE Computer Society, (2010)SmartCap: user experience-oriented power adaptation for smartphone's application processor., , , и . DATE, стр. 57-60. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment., , , , и . DAC, стр. 109:1-109:6. ACM, (2018)RISO: relaxed network-on-chip isolation for cloud processors., , , , и . DAC, стр. 38:1-38:6. ACM, (2013)ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations., , , , и . ASPLOS (3), стр. 71-85. ACM, (2024)