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Disambiguation of "Gupta, Naina"

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XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V.

, , , , , , and . IACR Cryptology ePrint Archive, (2018)

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Naina Daya

Naina Rastalsky

Naina Deibel

Nainapal

Jan Chandra Gupta

 

Other publications of authors with the same name

SoCFaSe: in quest for fast and secure SoC architectures. Nanyang Technological University, Singapore, (2023)MemEnc: A Lightweight, Low-Power, and Transparent Memory Encryption Engine for IoT., , and . IEEE Internet Things J., 8 (9): 7182-7191 (2021)PQC Acceleration Using GPUs: FrodoKEM, NewHope, and Kyber., , , and . IEEE Trans. Parallel Distributed Syst., 32 (3): 575-586 (2021)Exploiting the Leakage: Analysis of Some Authenticated Encryption Schemes., , , , and . SPACE, volume 10076 of Lecture Notes in Computer Science, page 383-401. Springer, (2016)In Quest for Fast and Secure SoC., and . VLSI-SoC, page 1-2. IEEE, (2021)Post-Quantum Secure Boot., , , , , and . DATE, page 1582-1585. IEEE, (2020)CRYSTALS-Dilithium on RISC-V Processor: Lightweight Secure Boot Using Post-Quantum Digital Signature., , and . ICCAD, page 1-7. IEEE, (2023)XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V., , , , , , and . IACR Cryptology ePrint Archive, (2018)EFFLUX-F2: A High Performance Hardware Security Evaluation Board., , , and . COSADE, volume 14595 of Lecture Notes in Computer Science, page 38-56. Springer, (2024)Towards Designing a Secure RISC-V System-on-Chip: ITUS., , , , , , and . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)