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A comparative study of arbitration algorithms for the Alpha 21364 pipelined router.

, , , , , and . ASPLOS, page 223-234. ACM Press, (2002)

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Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement, and . ACM Trans. Comput. Syst., 3 (1): 31-62 (1985)ZIP-IO: Architecture for application-specific compression of Big Data., , , and . FPT, page 343-351. IEEE, (2012)LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators., , , , and . ISPASS, page 316-318. IEEE, (2023)Architecture-Level Energy Estimation for Heterogeneous Computing Systems., , , , and . ISPASS, page 229-231. IEEE, (2021)Instruction Fetching: Coping with Code Bloat., , , , and . ISCA, page 345-356. ACM, (1995)Retrospective: Characterization of Processor Performance in the VAX-11/780., and . 25 Years ISCA: Retrospectives and Reprints, page 37-38. ACM, (1998)Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor., , , , , and . ISCA, page 191-202. ACM, (1996)Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes., , , , and . ISCA, page 38:1-38:16. ACM, (2023)SAM: Optimizing Multithreaded Cores for Speculative Parallelism., , , , and . PACT, page 64-78. IEEE Computer Society, (2017)Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor., , , and . ISCA, page 264-275. IEEE Computer Society, (2004)