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HLS-based fault tolerance approach for SRAM-based FPGAs.

J. Lojda, J. Podivinsky, M. Krcma, and Z. Kotásek. FPT, page 301-302. IEEE, (2016)

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Jakub Mácha

Analytische Theorien der Metapher: Untersuchungen zum Konzept der metaphorischen BedeutungJ. Mácha. Uni Hannover, (2009)

Jakub Kopycki

Jakub Limanowski

Jakub Hodek

Jakub Novák

Other publications of authors with the same name

HLS-based fault tolerance approach for SRAM-based FPGAs.J. Lojda, J. Podivinsky, M. Krcma, and Z. Kotásek. FPT, page 301-302. IEEE, (2016)Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation.J. Lojda, J. Podivinsky, and Z. Kotásek. EWDTS, page 1-6. IEEE Computer Society, (2017)FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation.J. Lojda, J. Podivinsky, O. Cekan, R. Panek, and Z. Kotásek. DSD, page 244-251. IEEE Computer Society, (2018)Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems.J. Podivinsky, O. Cekan, J. Lojda, and Z. Kotásek. DSD, page 487-494. IEEE Computer Society, (2016)The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications.J. Podivinsky, O. Cekan, M. Simková, and Z. Kotásek. DSD, page 312-319. IEEE Computer Society, (2014)Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis.J. Lojda, J. Podivinsky, and Z. Kotásek. EWDTS, page 1-7. IEEE, (2018)Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study.J. Podivinsky, O. Cekan, M. Krcma, R. Burget, T. Hruska, and Z. Kotásek. DSD, page 597-600. IEEE, (2019)Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards.O. Cekan, J. Podivinsky, J. Lojda, R. Panek, M. Krcma, and Z. Kotásek. DSD, page 506-513. IEEE, (2019)Hardening of Smart Electronic Lock Software against Random and Deliberate Faults.J. Lojda, R. Panek, J. Podivinsky, O. Cekan, M. Krcma, and Z. Kotásek. DSD, page 680-683. IEEE, (2020)Software Fault Tolerance: The Evaluation by Functional Verification.O. Cekan, J. Podivinsky, and Z. Kotásek. DSD, page 284-287. IEEE Computer Society, (2015)

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Disambiguation of "Podivinsky, Jakub"

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HLS-based fault tolerance approach for SRAM-based FPGAs.

Please choose a person to relate this publication to

Jakub Mácha

Jakub Kopycki

Jakub Limanowski

Jakub Hodek

Jakub Novák

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Podivinsky, Jakub"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML HLS-based fault tolerance approach for SRAM-based FPGAs.

Please choose a person to relate this publication to

Jakub Mácha

Jakub Kopycki

Jakub Limanowski

Jakub Hodek

Jakub Novák

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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HLS-based fault tolerance approach for SRAM-based FPGAs.