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The MareNostrum Experimental Exascale Platform (MEEP)., , , , , , и . Supercomput. Front. Innov., 8 (1): 62-81 (2021)Automated, inter-macro channel space adjustment and optimization for faster design closure., , и . SoCC, стр. 74-79. IEEE, (2017)Streaming FFT on REDEFINE-v2: an application-architecture design space exploration., , , , , , , и . CASES, стр. 127-136. ACM, (2009)Synthesis of application accelerators on Runtime Reconfigurable Hardware., , , , , , , и . ASAP, стр. 13-18. IEEE Computer Society, (2008)Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC., , и . DATE, стр. 130-135. IEEE, (2021)Symmetric $k$-Means for Deep Neural Network Compression and Hardware Acceleration on FPGAs., , , , и . IEEE J. Sel. Top. Signal Process., 14 (4): 737-749 (2020)TAD: time side-channel attack defense of obfuscated source code., , и . ASP-DAC, стр. 58-63. ACM, (2019)Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures., , , , и . ARC, том 5453 из Lecture Notes in Computer Science, стр. 204-215. Springer, (2009)XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage., , , , и . ASAP, стр. 179-186. IEEE, (2021)A Parallel Architecture for High Frame Rate Stereo using Semi-Global Matching., , и . BMVC, BMVA Press, (2017)