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Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference., , , , , , and . IEEE Micro, 42 (1): 89-98 (2022)3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression., , , , , , , , , and 1 other author(s). A-SSCC, page 1-3. IEEE, (2023)A Time-Memory-based CMOS Vision Sensor with In-Pixel Temporal Derivative Computing for Multi-Mode Image Processing., , , , , and . ESSCIRC, page 109-112. IEEE, (2023)A 65-nm RRAM Compute-in-Memory Macro for Genome Processing., , , , , , , , , and . IEEE J. Solid State Circuits, 59 (7): 2093-2104 (July 2024)FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro., , , , , and . ESSCIRC, page 405-408. IEEE, (2023)A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification., , , , , , , , and . ESSCIRC, page 89-92. IEEE, (2022)Stochastic implementation of the activation function for artificial neural networks., , , and . BioCAS, page 440-443. IEEE, (2016)Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention., , , , , , , and . ISCAS, page 1-4. IEEE, (2023)Implementation of STDP Learning for Non-volatile Memory-based Spiking Neural Network using Comparator Metastability., , and . AICAS, page 239-243. IEEE, (2019)A CMOS-based Resistive Crossbar Array with Pulsed Neural Network for Deep Learning Accelerator., , , and . AICAS, page 34-37. IEEE, (2019)