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Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders.

, , , , , , , , and . IEEE Des. Test, 40 (1): 85-95 (February 2023)

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Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications., , , , , and . FCCM, page 226. IEEE, (2020)OptiCPD: Optimization For The Canonical Polyadic Decomposition Algorithm on GPUs., and . IPDPS Workshops, page 403-412. IEEE, (2023)MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication., , , , and . VLSID, page 102-107. IEEE, (2022)Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs., , , , , , , , and . SiPS, page 1-6. IEEE, (2020)Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders., , , , , , , , and . IEEE Des. Test, 40 (1): 85-95 (February 2023)A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures., , , , , , , , , and . IEEE Commun. Surv. Tutorials, 24 (1): 524-556 (2022)IT Infrastructure Downtime Preemption using Hybrid Machine Learning and NLP., , , , and . FedCSIS (Position Papers), volume 6 of Annals of Computer Science and Information Systems, page 39-44. (2015)