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Design and verification of pipelined circuits with Timed Petri Nets., , и . Discret. Event Dyn. Syst., 33 (1): 1-24 (марта 2023)Hardware runtime verification of embedded software in SoPC., , , , и . SIES, стр. 171-176. IEEE, (2016)HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems., , и . AHS, стр. 249-256. IEEE, (2018)Extending Harmless architecture description language for embedded real-time systems validation., , и . SIES, стр. 223-231. IEEE, (2011)Improving processor hardware compiled cycle accurate simulation using program abstraction., , , и . SimuTools, стр. 186-194. ICST/ACM, (2014)Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design., , и . Petri Nets, том 12734 из Lecture Notes in Computer Science, стр. 55-75. Springer, (2021)Improving processor hardware compiled cycle accurate simulation using program abstraction., , , и . SimuTools, стр. 186-194. ICST/ACM, (2014)Instruction set simulator generation using HARMLESS, a new hardware architecture description language., , , , и . SimuTools, стр. 24. ICST/ACM, (2009)Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection., , , , и . EDCC, стр. 25-32. IEEE Computer Society, (2018)Device driver synthesis for embedded systems., , , , и . ETFA, стр. 1-8. IEEE, (2013)