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From program to hardware: A parallel architecture compiler., , , and . Microprocessing and Microprogramming, 30 (1-5): 467-474 (1990)A framework for offline optimization of energy consumption in real time multiprocessor system-on-chip., , and . ICECS, page 900-903. IEEE, (2009)Partitioning Reactive Data Flow Applications On Dynamically Reconfigurable Systems., and . VLSI-SOC, page 282-287. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Synthesis of dedicated SIMD processors., , , and . ASAP, page 416-427. IEEE, (1993)Rapid Development of Optimized DSP Code from a High Level Description Through Software Estimations., , , and . DAC, page 823-826. ACM Press, (1999)FPGA-based generic neural network architecture., , and . IES, page 1-4. IEEE, (2006)Energy Optimization of a Multi-bank Main Memory., , , and . SAMOS, volume 4017 of Lecture Notes in Computer Science, page 196-205. Springer, (2006)A semi-partitioned real-time scheduling approach for periodic task systems on multicore platforms., , and . SAC, page 1594-1601. ACM, (2012)Towards a multi-formalism framework for architectural synthesis: the ASAR project., , , , , , , , , and 4 other author(s). CODES, page 25-32. IEEE Computer Society, (1994)A SW/Configware Codesign Methodology for Control Dominated Applications., and . ASAP, page 56-64. IEEE Computer Society, (2005)