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Disambiguation of "Valls, Javier"

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Fast- and Low-Complexity atan2(a, b) Approximation Tips and Tricks.

, , and . IEEE Signal Process. Mag., 34 (6): 164-169 (2017)

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Javier Valls

Alvaro Valls

Alvaro Valls

Javier Manero

Javier Jáurequi

 

Other publications of authors with the same name

Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs., , , and . VLSI Signal Processing, 47 (2): 183-187 (2007)FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices., , , , , and . IEEE Trans. Educ., 50 (3): 229-235 (2007)Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems., , , and . CSSP, 38 (4): 1793-1810 (2019)50 Years of CORDIC: Algorithms, Architectures, and Applications., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1893-1907 (2009)Power analysis and estimation tool integrated with XPOWER., , , and . FPGA, page 259. ACM, (2004)A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems., , , , and . PIMRC, page 531-535. IEEE, (2004)Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (11): 2256-2267 (2014)Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes., , , and . J. Signal Process. Syst., 66 (2): 99-104 (2012)Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes., , , and . J. Signal Process. Syst., 68 (2): 139-149 (2012)Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain., , and . Int. J. Reconfigurable Comput., (2014)