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Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems.

, , and . ICPP (1), page 326-330. Pennsylvania State University Press, (1990)

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Layout-aware Illinois Scan design for high fault coverage coverage., , , and . ISQED, page 683-688. IEEE, (2010)STEP: a unified design methodology for secure test and IP core protection., , , , and . ACM Great Lakes Symposium on VLSI, page 333-338. ACM, (2012)Write scheme for multiple Complementary Resistive Switch (CRS) cells., , , and . PATMOS, page 1-5. IEEE, (2014)On the synthesis of attack tolerant cryptographic hardware., , , , , and . VLSI-SoC, page 286-291. IEEE, (2010)A new class of bit- and byte-error control codes., and . IEEE Trans. Inf. Theory, 38 (5): 1617-1623 (1992)Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model., , and . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 546-558 (1993)Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3559-3567 (2008)Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems., and . IEEE Trans. Computers, 36 (3): 344-355 (1987)A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications., , , and . SoCC, page 309-312. IEEE, (2007)Bit-Serial Generalized Median Filters., , and . ISCAS, page 85-88. IEEE, (1994)