( en | de | ru )

 

Disambiguation of "Yu, Chang-Hyo"

Author of the publication

copydeleteadd this publication to your clipboard
2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 42-44. IEEE, (2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hyo-Chang Nam

Yu-Sung Chang

Ta Yü Chang

Yu-Yen Chang

Chang-Yu Lin

 

Other publications of authors with the same name

An efficient texture cache for programmable vertex shaders., , and . ISCAS, IEEE, (2006)A Memory-Efficient Unified Early Z-Test., , and . IEEE Trans. Vis. Comput. Graph., 17 (9): 1286-1294 (2011)A hardware-like high-level language based environment for 3D graphics architecture exploration., , , , , , , , , and 3 other author(s). ISCAS (2), page 512-515. IEEE, (2003)Tessellation-enabled shader for a bandwidth-limited 3D graphics engine., , , and . CICC, page 367-370. IEEE, (2008)A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems., , , and . CICC, page 579-582. IEEE, (2007)A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine., , , , , , , , , and . IEEE J. Solid State Circuits, 43 (5): 1247-1259 (2008)A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1369-1382 (2009)A 3D graphics processor with fast 4D vector inner product units and power aware texture cache., , , and . CICC, page 539-542. IEEE, (2008)A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine., , , , , , , and . ISSCC, page 276-602. IEEE, (2007)A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter., and . ISCAS (2), page 724-727. IEEE, (2003)