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Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (10): 2317-2330 (2019)Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips., , , , , and . MOCAST, page 1-4. IEEE, (2019)Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs., , , , , and . CoRR, (2019)Exploiting Neural-Network Statistics for Low-Power DNN Inference., , and . CoRR, (2023)Coding approach for low-power 3D interconnects., , and . DAC, page 23:1-23:6. ACM, (2018)Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels., , , , and . PATMOS, page 222-228. IEEE, (2018)Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D Integration., and . PATMOS, page 214-221. IEEE, (2018)Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs., , , , , and . DATE, page 37-42. IEEE, (2020)Edge effects on the TSV array capacitances and their performance influence., , and . Integr., (2018)Edge effect aware low-power crosstalk avoidance technique for 3D integration., , and . Integr., (2019)