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Clock Number Reduction Abstraction on CEGAR Loop Approach to Timed Automaton.

, , and . ICNC, page 235-241. IEEE Computer Society, (2011)

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Bidirectional Translation between OCL and JML for Round-Trip Engineering., , , and . APSEC (2), page 49-54. IEEE Computer Society, (2013)Specification of Real-Time Systems Using a Timed Automata Model with Shared Variables and Verification of Partial-Deadlock Freeness., , , , and . ICPP Workshops, page 576-581. IEEE Computer Society, (1999)Synthesis of Protocol Entities' Specifications from Service Specifications in a Petri Net Model with Registers., , , and . ICDCS, page 510-517. IEEE Computer Society, (1995)Fault Localization with DNN-based Test Case Learning and Ablated Execution Traces., , , and . ISE@APSEC, volume 3655 of CEUR Workshop Proceedings, CEUR-WS.org, (2023)Tool to Automatically Generate a Screen Transition Model Based on a Conceptual Model., , , , and . JCKBSE, page 158-167. Springer, (2018)Approach to Testing Many State Machine Models in Education., , and . CSEDU (1), page 481-488. SciTePress, (2019)Deriving Protocol Specifications from Service Specifications in Extended FSM Models., , , and . ICDCS, page 141-148. IEEE Computer Society, (1993)Automated inspection method for an STAMP/STPA - Fallen Barrier Trap at Railroad Crossing -., , , and . KES, volume 159 of Procedia Computer Science, page 1165-1174. Elsevier, (2019)A Bounded Model Checker for Timed Automata and Its Application to LTL Properties., , , , , , and . KES, volume 207 of Procedia Computer Science, page 532-541. Elsevier, (2022)Reducing Syntactic Complexity for Information Extraction from Japanese Requirement Specifications., , , and . APSEC, page 387-396. IEEE, (2022)