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Disambiguation of "Calazans, Ney Laert Vilar"

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BAT-Hermes: A transition-signaling bundled-data NoC router.

, , , and . LASCAS, page 1-4. IEEE, (2015)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Loreto Vilar

Ignazio Vilardi

Sisi Alexandra Vilardi

Fabio Vilardi

David Vilar Torres

 

Other publications of authors with the same name

Evaluating the robustness of secure triple track logic through prototyping., , , , , and . SBCCI, page 193-198. ACM, (2008)Automated Synthesis of Cell Libraries for Asynchronous Circuits., , , , and . SBCCI, page 16:1-16:7. ACM, (2014)Design and analysis of the HF-RISC processor targeting voltage scaling applications., , , , , , and . SBCCI, page 1-6. IEEE, (2016)Go functional model for a RISC-V asynchronous organisation - ARV., and . ICECS, page 381-384. IEEE, (2017)Design and Analysis of Testable Mutual Exclusion Elements., , , , , , and . ASYNC, page 124-131. IEEE Computer Society, (2015)Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications., , , , , and . ASYNC, page 11-18. IEEE Computer Society, (2016)Blade - A Timing Violation Resilient Asynchronous Template., , , , , , , , , and . ASYNC, page 21-28. IEEE Computer Society, (2015)A design flow for physical synthesis of digital cells with ASTRAN., , , , and . ACM Great Lakes Symposium on VLSI, page 245-246. ACM, (2014)Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes., , and . SBCCI, page 1-6. IEEE, (2012)Rate-based scheduling policy for QoS flows in networks on chip., and . VLSI-SoC, page 140-145. IEEE, (2007)